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Circuit topologies and measured behavior: filters, semiconductors, op-amps, oscillators, feedback, conversion, and FPGA logic.

passive networks · diodes · transistors · op-amps · oscillators & modulation · sensing & control · audio · ADC & DAC · digital logic & FPGAs · physical limits

topologyoperating regiontransfer behaviorloading + limits

Reading rule. A schematic fixes connectivity; the component model fixes local behavior; feedback and loading fix the realized transfer. Every figure below pairs a circuit with the voltage, waveform, spectrum, or state it produces.

Passive networks: division, filtering & resonance

A 22 kiloohm and 10 kiloohm voltage divider connected to a 3 volt source — **Divider.** The output is a fraction of the input, but only until a load becomes a third parallel branch.

Series resistor and shunt capacitor RC low-pass circuit — **One-pole low-pass.** The resistor limits charge flow; the capacitor stores the output voltage.

Voltage divider. \(V_{\rm out}=V_{\rm in}R_2/(R_1+R_2)\). Seen from the output, \(V_{\rm th}=V_{\rm out}\) and \(R_{\rm th}=R_1\parallel R_2\); with load \(R_L\), replace \(R_2\) by \(R_2\parallel R_L\).

Capacitor dynamics. \(I=C\,\dd V/\dd t\), \(Z_C=1/(i\omega C)\), and \(\tau=RC\). A low-pass has \(H_{\rm LP}=1/(1+i\omega RC)\); a high-pass has \(H_{\rm HP}=i\omega RC/(1+i\omega RC)\). Both turn at \(f_c=1/(2\pi RC)\), where the gain is \(1/\sqrt2\) and the asymptotic slope is \(20\,\mathrm{dB/decade}\).

Square wave passing almost unchanged through an RC circuit when frequency is low — \(T/2\gg\tau\): the capacitor reaches each new level, so \(V_{\rm out}\approx V_{\rm in}\).

Exponential charging and discharging response to a square wave — \(T/2\sim\tau\): each edge exposes exponential charging and discharging.

Triangle-like integrated output from a high frequency square wave — \(T/2\ll\tau\): little charge moves per half-cycle; the low-pass approximately integrates.

RC high-pass differentiator circuit — **Differentiator.** For \(\omega RC\ll1\), \(V_{\rm out}\approx RC\,\dd V_{\rm in}/\dd t\): edges become pulses.

RC low-pass integrator circuit — **Integrator.** For \(\omega RC\gg1\), \(V_{\rm out}\approx (RC)^{-1}\int V_{\rm in}\,\dd t\): a square tends toward a triangle.

Series RLC circuit with output measured across the resistor — **Series resonance.** Across \(R\), the response is band-pass: maximum current and zero reactive phase at \(f_0\).

Oscilloscope trace showing the RLC circuit selecting a sinusoidal harmonic from a square wave — **Harmonic selection.** Yellow is the square-wave drive; cyan is the resonant sinusoid extracted from its spectrum.

Resonance. \(f_0=1/(2\pi\sqrt{LC})\). The half-power points satisfy \(|V|=|V|_{\max}/\sqrt2\); \(Q=f_0/\Delta f\). Higher \(Q\) gives narrower selection and longer ringing. A square wave contains odd harmonics, so shifting the drive frequency moves successive harmonics through the same resonance.

Oscilloscope trace showing phase reversal and partial destructive addition in an RLC response — **Off resonance.** Harmonic components arrive with phase and amplitude that partially cancel.

Oscilloscope trace showing constructive harmonic addition in an RLC response — **Near constructive alignment.** The same network reshapes the square wave by weighting and phasing its harmonics.

Diodes: one-way, piecewise nonlinear behavior

Piecewise silicon model. The diode is open while \(V_A-V_K\lt V_D\), and conducting with nearly fixed \(V_A-V_K\approx V_D\) once on; \(V_D\) is commonly about \(0.6\,\mathrm V\) but depends on device, current, and temperature. Always include a resistor or other impedance that limits forward current.

Animated half-wave rectifier showing current on positive cycles and no current on negative cycles — **Half-wave rectifier.** One polarity produces load current; the other sees an open circuit. \(V_{\rm out}\approx\max(0,V_{\rm in}-V_D)\).

Diode clamp circuit with input resistor and diode to ground — **Clamp.** The output follows the input until the diode turns on, then stays near the reference plus one diode drop.

Clamp and protection. A diode to \(V_{\rm ref}\) limits \(V_{\rm out}\) near \(V_{\rm ref}\pm V_D\); the series resistor absorbs the excess voltage and limits clamp current. Reverse the diode to reverse the clipped polarity. LEDs obey the same current-limit requirement: \(R=(V_{\rm supply}-V_F)/I_{\rm LED}\).

Transistors: switching, buffering & gain

NPN regime	First-order condition	Circuit meaning
cutoff	\(V_{BE}\lt0.6\,\mathrm V,\ I_C\approx0\)	open switch
forward active	\(V_{BE}\approx0.6\,\mathrm V,\ I_C\approx\beta I_B,\ V_C\gt V_B\)	controlled current / analog gain
saturation	load prevents \(\beta I_B\); \(V_{CE}\) small	closed switch

NPN emitter follower with collector at 5 volts and output at emitter — **Emitter follower.** \(V_{\rm out}\approx V_{\rm in}-0.6\,\mathrm V\); voltage gain near one, current gain large.

NPN low-side transistor switch driving an LED — **Low-side switch.** Cutoff leaves the LED dark; saturation pulls the load current to ground.

Biased common-emitter BJT amplifier with collector and emitter output taps — **Common-emitter.** The divider sets DC bias; the capacitor couples AC; the collector output is amplified and inverted.

Active-region amplifier. Bias the transistor so the whole waveform stays between cutoff and saturation. With collector resistor \(R_C\) and unbypassed emitter resistance \(R_E\), \(A_v\approx-R_C/R_E\): increasing base voltage raises current, increasing the drop across \(R_C\), so collector voltage falls.

Current driver. A control signal supplies only base or gate drive; the load current comes from the load supply. A flyback diode is mandatory across inductive loads. For MOSFETs, gate threshold is not the fully-on voltage: check \(R_{DS(on)}\) at the available gate drive, current, switching loss, and thermal resistance.

Operational amplifiers: feedback creates functions

Ideal negative-feedback rules. \(I_+=I_-=0\), and while the output remains unsaturated \(V_+\approx V_-\). The open-loop relation \(V_{\rm out}=A(V_+-V_-)\) has enormous \(A\); negative feedback moves the output until the input difference is nearly zero.

Non-inverting operational amplifier with 22 kiloohm feedback and 10 kiloohm ground resistor — **Non-inverting.** \(A_v=1+R_f/R_g\); input impedance is high and polarity is preserved.

Inverting operational amplifier with 22 kiloohm feedback and 10 kiloohm input resistor — **Inverting.** The (-) node is a virtual ground; \(A_v=-R_f/R_{\rm in}\).

Feedback network	Ideal function
output directly to (-)	follower: \(V_{\rm out}=V_{\rm in}\)
several \(V_i\) through \(R_i\) to (-)	summer: \(V_{\rm out}=-R_f\sum_iV_i/R_i\)
matched ratios on both inputs	difference: \(V_{\rm out}=G(V_2-V_1)\)
sensor current into (-)	transimpedance: \(V_{\rm out}=-I_{\rm in}R_f\)
capacitor in feedback	integrator: \(V_{\rm out}=-(R_{\rm in}C)^{-1}\int V_{\rm in}\,\dd t\)
capacitor at input	differentiator: \(V_{\rm out}=-R_fC\,\dd V_{\rm in}/\dd t\)

Phototransistor transimpedance amplifier with resistor feedback — **Photodetector front end.** Feedback converts sensor current to voltage without letting the sensor node move far.

Operational amplifier used open-loop as a comparator against ground — **Comparator.** With no negative feedback, the output selects a rail according to the sign of \(V_+-V_-\): a one-bit ADC.

Inverting Schmitt trigger with positive feedback — **Schmitt trigger.** Positive feedback creates distinct rising and falling thresholds, suppressing chatter from noisy crossings.

Operational amplifier relaxation oscillator with capacitor and Schmitt feedback — **Relaxation oscillator.** The capacitor ramps between the Schmitt thresholds, forcing the output to alternate rails.

Hysteresis and oscillation. If feedback returns a fraction \(\alpha\) of symmetric \(\pm V_{\rm sat}\), thresholds are \(\pm\alpha V_{\rm sat}\). With an RC charging path, \[f=\left\{2RC\ln\!\left(\frac{1+\alpha}{1-\alpha}\right)\right\}^{-1}.\]

Real limits. Output swing stops near the rails; input common-mode range is finite; output current, gain-bandwidth, slew rate \(\max|\dd V_{\rm out}/\dd t|\), bias current, and offset are finite. Once a demanded output violates any limit, \(V_+\approx V_-\) no longer applies.

Oscillators, duty cycle & modulation

Standard 555 timer astable oscillator circuit — **555 astable.** The capacitor charges through \(R_1+R_2\) and discharges through \(R_2\), crossing \(V_{CC}/3\) and \(2V_{CC}/3\).

555 timer astable oscillator with diode-separated charge and discharge paths — **Independent paths.** A steering diode separates charging and discharging resistances, extending duty-cycle control.

Standard timing. \[t_H=\ln2\,(R_1+R_2)C,\qquad t_L=\ln2\,R_2C,\qquad f=\frac{1}{\ln2\,(R_1+2R_2)C}.\] The ordinary topology therefore spends more than half its period high.

555 timer astable oscillator with a modulation input connected to the control pin — **Control-voltage modulation.** Moving the internal thresholds changes the time needed to reach them, hence the instantaneous frequency.

FFT of an unmodulated 555 square-wave oscillator showing carrier harmonics — **Unmodulated spectrum.** A square-like carrier appears as a harmonic comb rather than one spectral line.

FFT of a frequency-modulated 555 oscillator showing sidebands around the carrier harmonics — **Frequency modulation.** Modulation spreads energy into sidebands around the carrier and its harmonics; their spacing tracks the modulation frequency.

Sensing & closed-loop control

Temperature control block diagram with sensor and setpoint buffers feeding feedback, Peltier, and indicator stages — Closed loop: measure temperature, compare with a buffered setpoint, transform the error, drive the Peltier element, and let the new temperature return to the sensor.

Thermistor divider followed by an operational amplifier buffer — **Sensor.** The thermistor divider maps temperature to voltage; the follower prevents the controller from loading that mapping.

MOSFET low-side driver controlling current through a Peltier element — **Actuator.** The op-amp decides; the MOSFET supplies current. Current, dissipation, polarity, and heat sinking belong to this power stage.

Thermistor. For an NTC device, resistance decreases with temperature: \[R(T)=R_0\exp\!\left[\beta\left(\frac1T-\frac1{T_0}\right)\right].\] Put the thermistor in the upper or lower divider leg to select the sign of \(\dd V_{\rm sense}/\dd T\). Define \(e=V_{\rm set}-V_{\rm sense}\), then confirm the total loop sign is negative: a temperature rise must eventually command less heating or more cooling.

PID law. \[u(t)=K_Pe(t)+K_I\int e(t)\,\dd t+K_D\frac{\dd e}{\dd t}.\] P responds immediately but leaves finite error; I removes persistent offset but can wind up; D anticipates motion and adds damping but amplifies high-frequency noise.

Inverting proportional operational amplifier stage — P. \(V_P=-(R_{P2}/R_{P1})V_{\rm err}\): constant gain at all relevant frequencies.

Practical operational amplifier integral stage with capacitor and parallel resistor feedback — I. Capacitive feedback accumulates error; the parallel resistor bounds DC gain and limits wind-up.

Operational amplifier differentiator stage with input capacitor and resistor feedback — D. The input capacitor emphasizes changing error; practical bandwidth limits are needed to suppress noise.

Audio as a complete analog signal chain

Audio processing block diagram with source, buffers, amplifier, filter, summer, power stage, and speaker — A useful architecture separates voltage processing from power delivery: source → buffer/gain → filter → sum → current-capable output → speaker.

Two-input inverting operational amplifier summing circuit — **Mixer.** \(V_{\rm out}=-R_f(V_1/R_1+V_2/R_2+\cdots)\); each input resistor independently weights one channel.

Complementary NPN and PNP class B push-pull output stage driving a speaker — **Class-B output.** NPN sources the positive half and PNP sinks the negative half; neither conducts near zero, producing crossover distortion.

Impedance and power. A small-signal op-amp can produce the correct unloaded voltage yet current-limit into an \(8\,\Omega\) speaker. Buffers isolate high-impedance signal stages from low-impedance loads. Class-AB bias reduces the roughly \(1.2\,\mathrm V\) dead band at the cost of idle current and heat.

Spectrum. Filtering changes tone by weighting harmonics; clipping creates new high-frequency components. Equal voltage does not imply equal loudness because speaker and hearing response are frequency dependent.

Analog ↔ digital conversion

Quantization. An ideal \(N\)-bit converter divides \(0\) to \(V_{\rm ref}\) into \(2^N\) codes. One LSB is \(\Delta V=V_{\rm ref}/2^N\), ideal quantization error is at most \(\Delta V/2\), and code \(D\) represents about \(DV_{\rm ref}/2^N\). Accuracy, offset, linearity, noise, and conversion time are separate limits.

Flash analog-to-digital converter using a resistor ladder and three comparators — **Flash ADC.** A reference ladder creates \(2^N-1\) thresholds; all comparators decide in parallel—fast, but hardware-heavy.

Successive approximation ADC prototype with weighted trial voltage and comparator — **Successive approximation.** Try the MSB, compare, keep or clear it, then descend to the LSB: \(N\) decisions for \(N\) bits.

Three-bit R-2R resistor ladder digital-to-analog converter — **R–2R DAC.** Repeating only \(R\) and \(2R\) weights bits by halves; resistor matching determines linearity.

Digital interface. Parallel data exposes every bit simultaneously; serial data trades pins for protocol and latency. Logic thresholds are ranges, not ideal points: common \(5\,\mathrm V\) TTL treats inputs below \(0.8\,\mathrm V\) as LOW and above \(2.0\,\mathrm V\) as HIGH, but \(3.3\,\mathrm V\), \(1.8\,\mathrm V\), and CMOS families differ.

PWM as conversion. Switching between \(V_L\) and \(V_H\) with duty \(D\) gives average \(\bar V=DV_H+(1-D)V_L\). A low-pass or inertial load extracts the average; switching ripple and load current still require a filter and driver.

Digital logic & FPGAs

Hardware state. Combinational gates depend on present inputs; flip-flops capture state on a clock edge. In an FPGA, independent logic operates concurrently: counters, filters, interfaces, and state machines are spatial circuits, not instructions time-shared on one CPU core.

Four-bit FPGA counter with each output bit routed to a pin — **Counter as divider.** Bit \(k\) toggles at \(f_{\rm clk}/2^{k+1}\); the bus is one state register viewed at four binary weights.

FPGA debounce circuit with synchronizing flip-flops, change detector, counter, and output register — **Debounce.** Synchronize the asynchronous input, detect a transition, then accept it only after it remains stable for \(2^n\) clock cycles; \(t_{\rm stable}=2^n/f_{\rm clk}\).

FPGA quadrature decoder with two debounced inputs, state flip-flops, XOR logic, and direction output — **Quadrature decoder.** Two \(90^\circ\)-shifted channels encode motion; a state transition gives a count and which channel leads gives direction.

Physical I/O. A logical pin name has no electrical meaning until assigned to a package pin and I/O bank. Buttons and displays may be active-low; external logic must satisfy the bank's voltage, current, setup/hold, and asynchronous-input requirements.

Physical limits & observed behavior

Loading. A source with Thévenin pair \(V_{\rm th},R_{\rm th}\) driving \(R_L\) produces \(V_L=V_{\rm th}R_L/(R_{\rm th}+R_L)\). A \(50\,\Omega\) function generator, scope probe capacitance, next amplifier, or speaker is part of the circuit once connected.

Edges reveal hidden dynamics. A nominal square wave contains arbitrarily high harmonics; real bandwidth, slew rate, stray capacitance/inductance, and transmission-line reflections round or ring its edge. Even the probe has an RC divider that must be compensated.

Undercompensated oscilloscope probe response with a rounded square-wave edge — **Undercompensated.** Too much effective probe capacitance: high frequencies are attenuated, so edges round.

Correctly compensated oscilloscope probe response showing a flat square wave — **Compensated.** Probe and scope time constants match; the step is flat after a fast edge.

Overcompensated oscilloscope probe response with overshoot at the square-wave edge — **Overcompensated.** High frequencies are overemphasized, producing overshoot.

Observed behavior	Likely physical cause
amplitude falls when connected	loading, source resistance, output-current limit
output sticks at a rail	wrong feedback sign, invalid common-mode input, demanded swing beyond rails
rounded or triangular large signal	bandwidth, slew-rate, or RC limit
overshoot, ringing, oscillation	phase margin, stray \(L/C\), long return path, probe ground inductance
works unloaded but not into actuator	supply sag, heat, shared-ground drop, current or power rating
digital transitions multiply	contact bounce, asynchronous sampling, undefined threshold, noise

Datasheet boundary. Exact package and pinout; recommended operating conditions; absolute maximums; input/output voltage and current; output swing; common-mode range; bandwidth, slew, and switching time; thermal resistance; guaranteed min/max. Typical curves explain behavior but do not guarantee it.

Circuit figures and measured traces are from the UChicago PHYS 226 electronics laboratory; course logistics and apparatus-specific instructions are omitted.